As a conventional semiconductor memory device of this type, a cell transistor as shown schematically in FIG. 22 is known as a nonvolatile semiconductor memory device for storing two-bit information per cell. On a substrate in a region where a channel is formed between diffusion regions 12A and 12B provided in the surface of a substrate 11, an insulating film 13 and a control gate electrode 15 are provided, and insulating films 14 and word line electrodes 16 are provided on both sides of the insulating film 13 and the control gate electrode 15.
As memory cells of this type, those in the following nonpatent document 1 and following patent documents 1 to 5, and the like, for example, are referred to. As a memory that can store two bits on both sides of a charge trapping film immediately below a gate electrode independently, those in the following patent documents 6 to 9 are referred to.
Further, a configuration as shown in FIG. 23 is proposed as another configuration of the memory cell for storing two bits per cell. According to a description in the following patent document 9, for example, the nonvolatile memory of an MONOS structure having an insulating film (which will be referred to as an ONO (oxide-nitride-oxide-film) in which a silicon dioxide film, a silicon nitride film, and a silicon dioxide film are stacked atop one another on a substrate in this stated order as the gate insulating film 14 can store two-bit data per cell in the charge trapping film (silicon nitride film) sandwitched between the silicon dioxide films immediately below the gate electrode. In an EEPROM (Electrically Erasable and Programmable ROM) memory cell having the charge trapping film and nodes for storing two bits per cell, two individual bits or a left Node 1 and a right Node 2 are formed in a region spatially separated in the charge trapping region. Reading of two bits (in storage nodes) is performed in a direction opposite to the direction of its writing. For writing to the node 2 in the charge trapping film in the ONO film 14, positive voltages for writing are applied to the gate electrode 16 and the drain diffusion region 12B, the source diffusion region 12A is grounded, and sufficiently accelerated hot electrons are injected into a region in the charge trapping film in the ONO film 14, adjacent to the drain diffusion region 12B. Then, reading of a stored bit is performed in a direction opposite to the direction of writing: in order to perform reading, positive voltages are respectively applied to the gate electrode 16 and the source diffusion region 12A, and the drain diffusion region 12B is grounded. For erasure in the memory cell, an appropriate erasure voltage is applied to the gate electrode 16, for example. Then, in order to perform erasure in the Node 2, an erasing voltage is applied to the drain diffusion region 12B, and in order to perform erasure in the Node 1, the erasing voltage is applied to the source diffusion region 12A, thereby ejecting electrons from the charge trapping film. As described above, by setting predetermined gate voltage, and predetermined drain and source voltages, two bits can be stored on both sides of the charge trapping film immediately below the gate electrode, independently.
Next, a two-bit/cell MONOS memory device described in the following nonpatent document 1 will be described in detail.
The following nonpatent document 1 discloses a sectional view and an equivalent circuit of a MONOS memory having a two-bit-per-cell configuration and bias conditions at the times of writing, erasing and reading operations, as shown in FIGS. 24A through 24C.
A memory cell includes a pair of impurity diffusion regions (a pair of bit lines) provided in the surface of a substrate, a control gate CG provided on the silicon dioxide film on the surface of the substrate between the diffusion regions, and word lines WL on the ONO film provided on both sides of the silicon dioxide film on the surface of the substrate, extending in a direction orthogonal to the control gate. Writing to nodes (programming) is performed by source-side hot-electron injection, and erasure is performed by hot hole injection.
According to the following nonpatent document 1, respective storage sites under a word line WL[j] on the right hand side of a control gate CG[I+2n] are programmed in parallel. A bit line BL[I+2n−1] is set at a ground potential, a bit line BL[I+2n] is biased to 5.0 V, and a word line WL[j] is biased to 9.0 V. The control gate CG[I+2n] is biased to 1.0V/0.0V so as to induce/inhibit source-side hot-electron injection. Information stored on the right hand side of the control gate is erased by hot hole injection brought about by the bias conditions in FIG. 24C. At the time of reading, on the other hand, the bit line[I+2n−1] is biased to 1.5V, bit line [i+2n] is biased to 0.0V, word line WL[j] is biased to Vread, and the control gate CG[I+2n] is biased to 1.5V. In order to program/erase storage sites on the left hand side of the control gate CG[I+2n], the bias conditions for the bit line BL[I+2n−1] and the BL[I+2n] are exchanged. Reading of respective bits of the memory cells is performed by application of reverse reading, as shown in FIG. 24C.
[Nonpatent Document 1]
“A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection”, 2002 Symposium on VLSI technology Digest of a Technical Papars, p206-207.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-230332A (p19, FIG. 27)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-26149A (p16, FIG. 23)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2001-357681A (pp 6-7, FIG. 2 and FIG. 3)
[Patent Document 4]
U.S. Pat. No. 6,399,441
[Patent Document 5]
U.S. Pat. No. 6,388,293
[Patent Document 6]
U.S. Pat. No. 6,011,725
[Patent Document 7]
U.S. Pat. No. 6,256,231
[Patent Document 8]
Japanese Patent Kokai Publication No. JP-P2001-156189A (p2, FIG. 1)
[Patent Document 9]
Japanese Patent Kohyo Publication No. JP-P2001-512290A (pp45-47, FIG. 2)